multiprocessor MicroENgine

 

Western Digital Pascal Microengine-Based Systems

Updated on 12 July 2010.

I have five computers based on the Western Digital MicroEngine hardware pascal chipset and UCSD III P-system operating system with its hardware semaphores and pascal p-codes


Three are Western Digital prototype Modular Microengines  (WD-900 series) with 350Mb drives and 8" floppies.These are not currently operative, but are complete. They were physically damaged in transit from the US. These were the machines used by Dave Fisher and his team (including Joyce Tokar) at Gensoft to create and get certified the Ada 17.2 that was the first Ada to be certified in a microsystem. Gensoft Ada then went on to become Prime and Data General Ada, hosted within the original Microengine simulator! All floppies and tapes used for this system are still held, as well as the original Certificate and a formal zero-priced museum and conservation licence for UCSD Pascal III for the MicroEngines from the Regents of UCSD.


The original WD Microengine single computer board was used in canberra for the Australian Ortex series of computers, which ran a multiuser version of USCD 3 written by Bob Lunn from Melbourne, and became a successful foundation for a vertical market pharmacy system marketed throughout Australia in the 1980s.


The most distinctive system is a compete Pascal 100 based S-100 system in an Ithaca Intersystems full front panel box. It is still booting sweetly and running well (reconfirmed on 1 7 2010). This is a dual processor connected dual board set made by Digicomp Research of Terrace Hill Ithaca NY, which was steadily expanded to encompass their own memory and IO boards, and eventually to their own 68000 cpu with a fully configured Telesoft Ada system (the one emergent from UCSD Professor Ken Bowles' second enterprise).


The S-100 bus box adopted by Digicomp Research was a full front panel Ithaca Intersystems DPS1 and the Ithaca Intersystems FDC-1 floppy disc disc card was also used. Digicomp designed their own MFIO board and memory for this system, which complied with the IEEE-696 Standard. There are now excellent collections of manuals for most of these cards and bus details online (eg. here and here).


The main CPU is a  dual processor Z80 plus MicroEngine Chipset with a bipolar ROM for memory mapping to allow the Z80 to address the full IEEE 24 bit bus address space through an 8k window. Clocking can be adjusted by a plug in clock sub board. Standard settings are for 2MHZ, the system I hold has been run (remarkably) reliably at up to 3MHz,


The memory boards are a mix of 256kb Digicomp Research and Ithaca and Cromemco boards, 384kb are in the bus at present and the UCSD III is managed by a small startup program which creates and format the top 256kb as a Ram disc for UCSD, so that the entire system can be run from ram disc.


The ram disc was implemented by Tom Evans in Melbourne by an extension to the Z80 bios accessing the memory map, and the MicroEngine is set up to use all the Z80 IO with the Z80 as the IO processor. The MicroEngine accesses the bus directly for memory. It ran at 2.5Mhz and did 5000 task swaps a second in Pascal, using the appropriate semaphores in the microcode in a simple task swapping program. It could be (and frequently was)  pushed up to 3MHz by changing the clock crystal, probably the first overclocking hack for a 16 bit processor.


A Godbout System Support 1 S-100 board has been used to mount an AMD 9511 Floating Point Accelerator chip. The IO and bus interface chips died, so this is not currently operative  (however it previously operated with a range of languages that provided support for the 9511, these included Structured Algol, Gordon Eubanks' original EBasic, Microsoft Fortran (with two different proprietary commercial support libraries). The performance of the Z80 and the Microengine cpus is reported for a set of simple benchmarks by in : WIGAN, M. R. (1982) BASIC, FORTRAN, S-ALGOL and Pascal benchmarks on microcomputers, including the effects of floating point processor assistance. National Conference on Microcomputer Software. Canberra, ACT, MICSIG, Australian Computer Society (download here).


The last board is a complete  additional computer, containing a T11 DEC chip and 64k of memory. This runs a complete http://www.computer.museum.uq.edu.au/RT11.html, once again inheriting the device drives handled by  the Z80. RT11 is booted from a CP/M disc, and using the ram disc bios (written by Tom Evans)this allows the RT11 to have a 328k Ram disc as well as being able to access to the three 1mb 8" double sided double density Qume and YE Data 8" floppy drives


These three drives reside in a separate self powered box connected by ribbon cables. This same box is used with a 286 AT system and a Microsolutions ISA Bus card to read, write and format a huge range of CP/M and related formats on 8" single and double sided floppies.


This 4 cpu S100 system has been running in this form since about 1982-3. It still runs all barring the 9511 support for the Z80/cpm languages mentioned, although the 9511 chip is still here it requires some AMD 8 bit bus buffer chips to be replaced on the board before it can be deployed again, due to a bus shortout (not unusual in early S100 systems).


The logical successor to this innovative system was the Three Rivers PERQ, which was a variable microcode machine, optimised in microcode execution in Pascal faster than in Assembler. This has resonances with the later microcode development oriented systems AFC3200 and Orion discussed on the Microcomputer History page.